1) Field of the Invention
The present invention relates to a synchronous controlling unit and a synchronous control method that performs clock synchronization to thereby allow serial transmission between units that are operated at different frequencies.
2) Description of the Related Art
FIG. 7 is a structural block diagram of a conventional information processing system. The information processing system shown in FIG. 7 includes a clock controlling unit 10, a unit 20, and a unit 30. The clock controlling unit 10 generates clock signals CL at predetermined timing as shown in FIG. 8, and supplies the clock signals CL to the unit 20 and the unit 30.
The unit 20 is, for example, a main storage, and is operated by the clock signals CL from the clock controlling unit 10. On the other hand, the unit 30 is, for example, a CPU, and is operated by the same clock signals CL.
In this way, in the information processing system shown in FIG. 7, the unit 20 and the unit 30 are operated by the clock signals CL at the same frequency, bringing about a synchronous state. With the use of this synchronization, serial transmission of signals and data is carried out between the unit 20 and the unit 30.
The unit 20 includes a one-bit counter 21. As shown in FIG. 8, the counter 21 counts one bit every time the clock signals CL in one cycle are input, and outputs 0 and 1 alternately.
An AND circuit 22 implements the AND of an output from the counter 21 and a signal A. An AND circuit 23 implements the AND of an inverted output of the output from the counter 21 inverted by a NOT circuit 24 and a signal B. The signals A and B are signals that are serially transmitted between the units 20 and 30.
An OR circuit 25 implements the OR of an output from the AND circuit 22 and an output from the AND circuit 23. A flip-flop (FF) circuit 26 is controlled by the clock signals CL from the clock controlling unit 10, and stores outputs from the OR circuit 25. The FF circuit 26 is used for serial transmission to an FF circuit 32 of the unit 30. The signals B and the signals A are alternately output from the FF circuit 26 in synchronization with the clock signals CL as shown in FIG. 8.
On the other hand, the unit 30 includes a one-bit counter 31, counts one bit every time clock signals CL in one cycle are input in a synchronous state with the counter 21, and outputs 0 and 1 alternately as shown in FIG. 8.
The FF circuit 32 is provided corresponding to the FF circuit 26 of the unit 20, is controlled by the clock signals CL from the clock controlling unit 10, and stores outputs from the FF circuit 26. The signals B and the signals A are alternately output from the FF circuit 32 in synchronization with the clock signals CL as shown in FIG. 8.
An AND circuit 33 implements the AND of an output from the counter 31 and an output from the FF circuit 32 (the signal A or the signal B). An AND circuit 34 implements the AND of an inverted output of the output from the counter 31 inverted by a NOT circuit 35 and an output from the FF circuit 32 (the signal A or the signal B).
An FF circuit 36 is controlled by the clock signals CL from the clock controlling unit 10, and stores outputs from the AND circuit 33. Signals A′ are output from the FF circuit 36, as shown in FIG. 8. An FF circuit 37 is controlled by the same clock signals CL, and stores outputs from the AND circuit 34. Signals B′ are output from the FF circuit 37, as shown in FIG. 8.
As described above, in the conventional information processing system, serial transmission is performed provided that the unit 20 and the unit 30 shown in FIG. 7 are synchronized with each other by the clock signals CL at the same frequency.
However, if the unit 20 and the unit 30 utilize clock signals at a frequency different from each other, carrying out serial transmission becomes difficult.